Field of the Invention
The present invention relates to an encoding circuit, an analog-to-digital (AD) conversion circuit, an imaging device, and an imaging system.
Description of Related Art
A so-called column analog-to-digital conversion (ADC) type solid state imaging device having an AD conversion function embedded in a column unit has been developed and commercialized. As one of the AD conversion schemes for implementing the AD conversion function, a single slope (SS) type AD conversion scheme is known. In the SS type AD conversion scheme, a voltage of a reference signal called a ramp wave that changes stepwise is compared with the voltage of a signal to be subjected to AD conversion. Thereby, a time interval (time axis magnitude/pulse width) corresponding to the signal voltage is generated. The AD conversion is performed by measuring the time interval with a reference clock.
A time-to-digital converter (tdc) SS type AD conversion scheme in which the reference clock of the single slope type AD conversion scheme has phase information to further improve the accuracy of AD conversion has been proposed. For example, a configuration using the tdc SS type AD conversion scheme is disclosed in Japanese Unexamined Patent Application, First Publication No. 2011-55196 and Japanese Unexamined Patent Application, First Publication No. 2014-64059. In this scheme, a time interval is measured using a reference clock and a plurality of clocks (multiphase clocks) having different phases compared with the reference clock. If this scheme is used, for example, the resolution is increased by 1 bit if there are 2 pieces of phase information. Likewise, for example, the resolution is increased by 2 bits if there are 4 pieces of phase information. Likewise, for example, the resolution is increased by 4 bits if there are 16 pieces of phase information. It is possible to increase the resolution by increasing the phase information. The phase information does not linearly increase in accordance with the increase in the resolution, but increases exponentially. In the column ADC type solid state imaging device using the tdc SS type AD conversion scheme, a latch circuit for latching the phase information of the multiphase clock is embedded in the column unit.
FIG. 37 shows a configuration of an encoding circuit in a tdc SS type AD conversion circuit of a first conventional example. The encoding circuit 1010a shown in FIG. 37 includes a clock generating unit 1018a, a latch unit 1108a, a counting unit 1101, and an encoding unit 1106a. 
The clock generating unit 1018a has a delay circuit 1100a in which a plurality of fully-differential delay circuits DE1 to DE8 are connected in a ring shape. The clock generating unit 1018a outputs a plurality of lower phase signals (lower phase signals CK1 to CK8 and lower phase signals xCK1 to xCK8) according to the output signals of the plurality of fully-differential delay circuits DE1 to DE8. The lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8 are clocks whose logic states change periodically. The lower phase signals xCK1 to xCK8 are signals obtained by inverting the lower phase signals CK1 to CK8. That is, the logic states of the lower phase signals xCK1 to xCK8 are opposite to the logic states of the lower phase signals CK1 to CK8.
The fully-differential delay circuits DE1 to DE8 have a first input terminal (+), a second input terminal (−), a first output terminal (+), a second output terminal (−), a first power supply terminal, and a second power supply terminal. The first input terminal (+) of the fully-differential delay circuit DE1 is connected to the first output terminal (+) of the fully-differential delay circuit DE8. The second input terminal (−) of the fully-differential delay circuit DE1 is connected to the second output terminal (−) of the fully-differential delay circuit DE8. The first input terminals (+) of the fully-differential delay circuits DE2 to DE8 are connected to the second output terminals (−) of the fully-differential delay circuits DE1 to DE7 of the previous stage, respectively. The second input terminals (−) of the fully-differential delay circuits DE2 to DE8 are connected to the first output terminals (+) of the fully-differential delay circuits DE1 to DE7 of the previous stage, respectively. Each of the fully-differential delay circuits DE1 to DE8 inverts the signal input to the first input terminal (+) and outputs the inverted signal from the second input terminal (−). Also, each of the fully-differential delay circuits DE1 to DE8 inverts the signal input to the second input terminal (−) and outputs the inverted signal from the first input terminal (+).
The signals output from the first output terminals (+) of the fully-differential delay circuits DE1 to DE8 are input to the latch unit 1108a as the lower phase signals CK1 to CK8. The signals output from the second output terminals (−) of the fully-differential delay circuits DE1 to DE8 are input to the latch unit 1108a as the lower phase signals xCK1 to xCK8. The fully-differential delay circuit DE1 further has a pulse input terminal. A start pulse StartP is input to the pulse input terminal of the fully-differential delay circuit DE1.
A power supply voltage VDD is applied to the first power supply terminals of the fully-differential delay circuits DE1 to DE8. A ground voltage GND is applied to the second power supply terminals of the fully-differential delay circuits DE1 to DE8. Each of the fully-differential delay circuits DE1 to DE8 applies a delay according to the difference between the voltages applied to the first power supply terminal and the second power supply terminal to the input signal. Each of the fully-differential delay circuits DE1 to DE8 generates output signals by delaying the input signals of the first input terminal (+) and the second input terminal (−). That is, each of the fully-differential delay circuits DE1 to DE8 generates a first output signal corresponding to a first input signal of the first input terminal (+) and a second output signal corresponding to a second input signal of the second input terminal (−). The second output signal is a signal obtained by inverting the first output signal.
The latch unit 1108a latches a plurality of lower phase signals (the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8) output from the clock generating unit 1018a at the timing at which a control signal CO is input.
The counting unit 1101 performs a count operation on the basis of any one of the plurality of lower phase signals (the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8). For example, the counting unit 1101 performs a count operation using the lower phase signal xCK8 output through the latch unit 1108a as a count clock. For example, the counting unit 1101 performs a count operation at the falling edge of the lower phase signal xCK8.
The encoding unit 1106a encodes states of the plurality of lower phase signals (the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8) latched by the latch unit 1108a. Thereby, the encoding unit 1106a obtains a binary number according to the states of the plurality of lower phase signals latched by the latch unit 1108a. 
Next, the operation of the encoding circuit 1010a will be described. FIG. 38 shows the waveforms of the start pulse StartP, the lower phase signals CK1 to CK8, and the lower phase signals xCK1 to xCK8. In FIG. 38, the horizontal direction indicates time and the vertical direction indicates voltage.
When the logic state of the start pulse StartP changes from the L (Low) state to the H (High) state, the delay circuit 1100a starts the transition operation. In this transition operation, the logic states of the signals output from the fully-differential delay circuits DE1 to DE8 constituting the delay circuit 1100a sequentially change. The counting unit 1101 starts a count operation simultaneously when the delay circuit 1100a starts the transition operation. Simultaneously with the start of the transition operation by the delay circuit 1100a, a reference signal generating unit (not shown) starts the generation of a reference signal (ramp wave). The level of the reference signal generated by the reference signal generating unit monotonically increases or decreases with the passage of time.
An analog signal to be subjected to AD conversion and a reference signal are input to a comparing unit (not shown). At the same time, the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8 are input to the latch unit 1108a. The lower phase signal xCK8 is input to the counting unit 1101 through the latch unit 1108a. The comparing unit performs a comparison process of comparing the analog signal to be subjected to AD conversion with the reference signal. The comparing unit completes the comparison process at the timing at which the reference signal satisfies a predetermined condition with respect to the analog signal, and outputs the control signal CO at that timing. Specifically, when the magnitude relation between the two signals input to the comparing unit is switched, the control signal CO is inverted.
At this time, the latch unit 1108a latches the logic states of the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8. Further, the counting unit 1101 latches the count value (a higher count value). The lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8 latched by the latch unit 1108a are encoded by the encoding unit 1106a (binary conversion). Thereby, lower data of the digital data is obtained. A higher count value latched by the counting unit 1101 constitutes higher data of the digital data. By combining the lower data and the higher data, digital data corresponding to the level of the analog signal can be obtained.
For example, as shown in FIG. 38, the states of the plurality of lower phase signals (the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8) latched by the latch unit 1108a (combinations of the logic states of the plurality of lower phase signals) are states 0 to 15. If the counting unit 1101 performs a count operation at the falling edge of the lower phase signal xCK8, the combinations of the logic states of the plurality of lower phase signals in periods obtained by dividing a period in which the counting unit 1101 performs one count operation (a period from the falling edge of the lower phase signal xCK8 to the next falling edge) into 16 equal parts correspond to states 0 to 15. States 0 to 15 correspond to encoded values 0 to 15 which are encoding results.
FIG. 39 shows a configuration of the encoding circuit 1010b in the tdc SS type AD conversion circuit of a second conventional example. The encoding circuit 1010b shown in FIG. 39 includes a clock generating unit 1018b, a latch unit 1108b, a counting unit 1101, and an encoding unit 1106b. 
Differences of the configuration shown in FIG. 39 from the configuration shown in FIG. 37 will be described. The clock generating unit 1018b includes a delay circuit 1100b in which a plurality of fully-differential delay circuits DE1 to DE8 are connected in a ring shape. The clock generating unit 1018b outputs a plurality of lower phase signals (lower phase signals CK2, CK4, CK6, and CK8 and lower phase signals xCK2, xCK4, xCK6, and xCK8) according to output signals of the plurality of fully-differential delay circuits DE1 to DE8.
The lower phase signal generated by the clock generating unit 1018b is the same as the lower phase signal generated by the clock generating unit 1018a shown in FIG. 37. That is, the clock generating unit 1018b generates the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8. The clock generating unit 1018b outputs only some of the plurality of generated lower phase signals (the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8) for latching by the latch unit 1108b. 
The latch unit 1108b latches the plurality of lower phase signals (the lower phase signals CK2, CK4, CK6, and CK8 and the lower phase signals xCK2, xCK4, xCK6, and xCK8) output from the clock generating unit 1018b at a timing at which the control signal CO is input.
The encoding unit 1106b encodes states of the plurality of lower phase signals (the lower phase signals CK2, CK4, CK6, CK8 and lower phase signals xCK2, xCK4, xCK6, and xCK8) latched by the latch unit 1108b. Thereby, the encoding unit 1106b obtains a binary number according to the states of the plurality of lower phase signals latched by the latch unit 1108b. 
The configuration shown in FIG. 39 is substantially the same as that shown in FIG. 37 except for the above points.
The operation of the encoding circuit 1010b shown in FIG. 39 is substantially the same as the operation of the encoding circuit 1010a shown in FIG. 37, except for the difference in the lower phase signal latched by the latch unit 1108b. FIG. 40 shows the waveforms of the start pulse StartP, the lower phase signals CK1 to CK8, and the lower phase signals xCK1 to xCK8. In FIG. 40, the horizontal direction indicates time and the vertical direction indicates voltage.
For example, as shown in FIG. 40, the states of the plurality of lower phase signals (the lower phase signals CK2, CK4, CK6, and CK8 and the lower phase signals xCK2, xCK4, xCK6, and xCK8) latched by the latch unit 1108b (combinations of the logic states of the plurality of lower phase signals) are states 0 to 7. When the counting unit 1101 performs a count operation at the falling edge of the lower phase signal xCK8, the combinations of the logic states of the plurality of lower phase signals in periods obtained by dividing a period in which the counting unit 1101 performs one count operation (a period from the falling edge of the lower phase signal xCK8 to the next falling edge) into 8 equal parts correspond to states 0 to 7. States 0 to 7 correspond to encoded values 0 to 7 which are encoding results.
When the AD conversion circuits of the first conventional example and the second conventional example are applied to the column ADC type solid state imaging device, the column ADC type solid state imaging device is configured as follows. The delay circuit 1100a or the delay circuit 1100b is arranged outside a column unit corresponding to the column of pixels. The comparing unit, the latch unit 1108a or the latch unit 1108b, the encoding unit 1106a or the encoding unit 1106b, and the counting unit 1101 are arranged inside the column unit. A pixel signal output from the pixel is input to the comparing unit as an analog signal to be subjected to AD conversion. When the control signal CO from the comparing unit is inverted, the plurality of lower phase signals from the delay circuit 1100a or the delay circuit 1100b are latched by the latch unit 1108a or the latch unit 1108b. The states of the plurality of lower phase signals latched by the latch unit 1108a or the latch unit 1108b are encoded by the encoding unit 1106a or the encoding unit 1106b. The encoded value and the count value of the counting unit 1101 are output as digital data of the AD conversion result.
However, the following encoding error may occur in the conventional encoding circuit and the AD conversion circuit using the encoding circuit. A similar encoding error may occur in the imaging device using the conventional AD conversion circuit and the imaging system using the imaging device.
In the encoding of a plurality of lower phase signals latched by the latch unit 1108a or the latch unit 1108b, a process of detecting a thermometer code (a predetermined logic state) used in the flash type AD conversion circuit is preferable. Further, it is preferable to perform this process in time series while changing the lower phase signal to be compared. In the thermometer code detection process, it is detected that the logic states of the two lower phase signals are predetermined states, for example, “10.” “0” corresponds to the L state of the signal. “1” corresponds to the H state of the signal.
A procedure of encoding by the encoding circuit 1010a shown in FIG. 37 will be described. FIG. 41 shows the waveforms of the start pulse StartP, the lower phase signals CK1 to CK8, and the lower phase signals xCK1 to xCK8 in the encoding circuit 1010a. In FIG. 41, the horizontal direction indicates time and the vertical direction indicates voltage.
In FIG. 41, the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8 shown in FIG. 38 are arranged to constitute a group of signals falling (changing from the H state to the L state) sequentially at predetermined time intervals. Specifically, the lower phase signals are arranged in the order of the lower phase signals xCK1, CK2, xCK3, CK4, xCK8, CK6, xCK7, CK8, CK1, xCK2, CK3, xCK4, CK5, xCK6, CK7, and xCK8.
As shown in FIG. 41, when a predetermined time (corresponding to the delay time for one of the fully-differential delay circuits DE1 to DE8) has elapsed from the change of the lower phase signal xCK1 from the H state to the L state, the phase signal CK2 changes from the H state to the L state. The lower phase signal xCK3 changes from the H state to the L state when a predetermined time has elapsed from the change of the lower phase signal CK2 from the H state to the L state. Thereafter, likewise, the lower phase signals CK4, xCK8, CK6, xCK7, CK8, CK1, xCK2, CK3, xCK4, CK8, xCK6, CK7, and xCK8 sequentially change from the H state to the L state.
In the signal group (signal string) in which the plurality of lower phase signals latched by the latch unit 1108a are arranged in the above-described order, the logic states of two continuous lower phase signals are sequentially detected. If it is detected that the logic states of two continuous lower phase signals are predetermined states (a thermometer code), the states of a plurality of lower phase signals are determined according to a position at which the states are detected.
For example, the position at which the logic state changes from the H state to the L state in the signal group is detected. The fact that the logic state changes from the H state to the L state is equivalent to the fact that a previous lower phase signal in the order of the lower phase signals constituting the signal group is the L state and the subsequent lower phase signal is the H state.
For example, the logic states of two continuous lower phase signals are sequentially detected from the bottom to the top of the signal group shown in FIG. 41. For example, in the case of state 7, in the signal group, the logic state changes from the H state to the L state between the lower phase signal CK8 and the lower phase signal xCK7. For the other states 0 to 6 and 8 to 15, the logic state changes from the H state to the L state between the two lower phase signals according to each state. That is, it is possible to determine states of a plurality of lower phase signals by detecting a position at which the logic states of the plurality of lower phase signals arranged as shown in FIG. 41 change.
Specifically, encoding is performed by performing the following processing of steps (1) to (16) in time series.
(Step (1)) . . . Determination related to state 15
The logic states of the lower phase signal xCK8 and the lower phase signal CK7 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 15.
(Step (2)) . . . Determination related to state 14
The logic states of the lower phase signal CK7 and the lower phase signal xCK6 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 14.
(Step (3)) . . . Determination related to state 13
The logic states of the lower phase signal xCK6 and the lower phase signal CK5 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 13.
(Step (4)) . . . Determination related to state 12
The logic states of the lower phase signal CK5 and the lower phase signal xCK4 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 12.
(Step (5)) . . . Determination related to state 11
The logic states of the lower phase signal xCK4 and the lower phase signal CK3 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 11.
(Step (6)) . . . Determination related to state 10
The logic states of the lower phase signal CK3 and the lower phase signal xCK2 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 10.
(Step (7)) . . . Determination related to state 9
The logic states of the lower phase signal xCK2 and the lower phase signal CK1 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 9.
(Step (8)) . . . Determination related to state 8
The logic states of the lower phase signal CK1 and the lower phase signal CK8 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 8.
(Step (9)) . . . Determination related to state 7
The logic states of the lower phase signal CK8 and the lower phase signal xCK7 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 7.
(Step (10)) . . . Determination related to state 6
The logic states of the lower phase signal xCK7 and the lower phase signal CK6 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 6.
(Step (11)) . . . Determination related to state 5
The logic states of the lower phase signal CK6 and the lower phase signal xCK8 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 5.
(Step (12)) . . . Determination related to state 4
The logic states of the lower phase signal xCK5 and the lower phase signal CK4 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 4.
(Step (13)) . . . Determination related to state 3
The logic states of the lower phase signal CK4 and the lower phase signal xCK3 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 3.
(Step (14)) . . . Determination related to state 2
The logic states of the lower phase signal xCK3 and the lower phase signal CK2 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 2.
(Step (15)) . . . Determination related to state 1
The logic states of the lower phase signal CK2 and the lower phase signal xCK1 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 1.
(Step (16)) . . . Determination related to state 0
The logic states of the lower phase signal xCK1 and the lower phase signal xCK8 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 0.
In steps (1) to (15), if it is determined that the state of each of the plurality of lower phase signals is not any of states 1 to 15, the state of each of the plurality of lower phase signals is state 0. Thus, step (16) is not particularly necessary.
A procedure of encoding by the encoding circuit 1010b shown in FIG. 39 will be described. FIG. 42 shows the waveforms of the start pulse StartP, the lower phase signals CK2, CK4, CK6, and CK8 and the lower phase signals xCK2, xCK4, xCK6, and xCK8 in the encoding circuit 1010b. In FIG. 42, the horizontal direction indicates time and the vertical direction indicates voltage.
In FIG. 42, the lower phase signals CK2, CK4, CK6, and CK8 and the lower phase signals xCK2, xCK4, xCK6, xCK8 shown in FIG. 40 are arranged to constitute a group of signals sequentially falling (changing from the H state to the L state) at predetermined time intervals. Specifically, the lower phase signals are arranged in the order of the lower phase signals CK2, CK4, CK6, CK8, xCK2, xCK4, xCK6, and xCK8.
As shown in FIG. 42, the phase signal CK4 changes from the H state to the L state when a predetermined time (corresponding to a delay time for two of the fully-differential delay circuits DE1 to DE8) has elapsed from the change of the lower phase signal CK2 from the H state to the L state. The lower phase signal CK6 changes from the H state to the L state when a predetermined time has elapsed from the change of the lower phase signal CK4 from the H state to the L state. Thereafter, likewise, the lower phase signals CK8, xCK2, xCK4, xCK6, and xCK8 sequentially change from the H state to the L state.
In the signal group (signal string) in which the plurality of lower phase signals latched by the latch unit 1108b are arranged in the above-described order, the logic states of two continuous lower phase signals are sequentially detected. When it is detected that the logic states of two continuous lower phase signals are predetermined states (thermometer codes), the states of a plurality of lower phase signals are determined according to a position at which the states are detected. For example, a position at which the logic state changes from the H state to the L state in the signal group is detected.
For example, the logic states of two continuous lower phase signals are sequentially detected from the bottom to the top of the signal group shown in FIG. 42. For example, in state 3, in the signal group, the logic state changes from the H state to the L state between the lower phase signal CK8 and the lower phase signal CK6. Also in the other states 0 to 2 and 4 to 7, the logic state changes from the H state to the L state between the two lower phase signals according to each state. That is, it is possible to determine the states of a plurality of lower phase signals by detecting a position at which the logic state of each of the plurality of lower phase signals arranged as shown in FIG. 42 changes.
Specifically, encoding is performed by performing the following steps (1) to (8) in time series.
(Step (1)) . . . Determination related to state 7
The logic states of the lower phase signal xCK8 and the lower phase signal xCK6 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 7.
(Step (2)) . . . Determination related to state 6
The logic states of the lower phase signal xCK6 and the lower phase signal xCK4 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 6.
(Step (3)) . . . Determination related to state 5
The logic states of the lower phase signal xCK4 and the lower phase signal xCK2 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 5.
(Step (4)) . . . Determination related to state 4
The logic states of the lower phase signal xCK2 and the lower phase signal CK8 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 4.
(Step (5)) . . . Determination related to state 3
The logic states of the lower phase signal CK8 and the lower phase signal CK6 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 3.
(Step (6)) . . . Determination related to state 2
The logic states of the lower phase signal CK6 and the lower phase signal CK4 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 2.
(Step (7)) . . . Determination related to state 1
The logic states of the lower phase signal CK4 and the lower phase signal CK2 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 1.
(Step (8)) . . . Determination related to state 0
The logic states of the lower phase signal CK2 and the lower phase signal xCK8 are compared. When there is a thermometer code at this position, the state of each of the plurality of lower phase signals is determined to be state 0.
In steps (1) to (7), if it is determined that the state of each of the plurality of lower phase signals is not any of states 1 to 7, the state of each of the plurality of lower phase signals is state 0. Thus, step (8) is not particularly necessary.
In the above-described encoding, the logic states of two lower phase signals are detected in time series on the basis of only one of the rising edge and the falling edge of the clock, which are the lower phase signals. Thus, even when the number of clocks generated by the clock generating unit 1018a or the clock generating unit 1018b is large, the circuit scale of the encoding circuit can be reduced and the configuration of the encoding circuit can be simplified.
However, if the tdc SS type AD conversion circuit using the delay circuit 1100a performs encoding by detecting the thermometer code, sixteen latch circuits for latching sixteen lower phase signals (the lower phase signals CK1 to CK8 and the lower phase signals xCK1 to xCK8) from the delay circuit 1100a are necessary in the latch unit 1108a. Thus, the circuit scale of the latch unit 1108a is increased. As a result, large drive capability is required for a latch control unit that controls the latch circuit.
When the drive capability of the latch control unit is not sufficient, it is difficult for the plurality of latch circuits to latch the phase information of the multi-phase clocks at substantially the same time. If a plurality of latch circuits do not latch the phase information of the multi-phase clocks at substantially the same time, an encoding error occurs. That is, AD conversion is not performed correctly.
Compared with the latch unit 1108a, the circuit scale of the latch unit 1108b is reduced. However, it is desirable to further reduce the circuit scale of the latch unit 1108b. 